Okay, hello everybody, welcome back. I'm glad that so many of you made it here this week

again because that means that I didn't scare everyone away two weeks ago. Today we were

talking, last lecture we stopped with micro-programming. This week we will talk about risk architectures.

To give everyone perspective what we are talking about because the lecture itself is called

architectures of supercomputers and now suddenly we are talking about processor architecture.

If we look at a modern supercomputer, these machines are huge, usually they fill a whole

building and they are comprised of individual compute nodes. These nodes are connected via

a network. The architecture and the hardware of these networks vary with the machines,

so currently we see very different networks, but anyhow any supercomputer consists of thousands

to tens of thousands of compute nodes. These compute nodes are not unlike your average

notebook but of course they are larger, more complex, faster, more expensive. These compute

nodes usually contain two sockets and each socket contains a multi-core CPU. If we look

closely into such a socket we would see a processor with multiple cores and in this

lecture we will look very closely into these cores to see what makes them fast, what makes

them different from CPUs which were designed 20 years ago. In the following lectures we

will then slowly take a step backwards, we will take a look at how single core designs

differ from multi-core designs, how single socket machines differ from multi-socket machines

and which complexity gets added when we add a network to the whole machine.

RISC architectures. What does this stand for? First of all RISC is an acronym which stands

for Reduced Instruction Set Computer. Does anyone know the opposite of RISC? Exactly,

very good. Interestingly the name SISC did not exist before RISC was introduced, so it

is sort of a marketing term to let former CPUs appear in a worse way than they actually

were. In the last lecture we were talking mainly about SISC because we were talking

about micro-programming and we were talking about how CPUs could execute complex assembly

instructions despite being rather simple structured internally. The solution was usually complex

instructions would be realized by micro-programming. RISC, even though RISC was a newer development,

first of all looks like a step backwards because it says we are not providing complex instructions,

we are just providing elementary and small machine instructions and we assume that the

programmer is able to compose these simple instructions to make complex programs work.

The reasoning behind that was that in the meantime compilers got better, so people were

not necessarily programming in assembly directly but they were using high level languages like

C. Even though today people usually would not call C a high level language back then,

it was a huge step forward. Also what makes RISC different is that address calculations

have to be done by the user or the entity who is writing the assembly code. If you look

at PCs like my notebook which is technically a SISC CPU, we will talk a bit about the difference

between SISC and RISC later on and how they relate to current designs but technically

my notebook understands a SISC instruction set and it can do very complex address calculations

and actually if you sometimes look at assembly code which is not doing memory access but

is actually doing calculations, you will sometimes see something like this. So does anyone know

what this LEA instruction means? Exactly. Why would anyone who is not planning to access

memory use this instruction? Exactly. Very good. So what this computes is actually it

takes the value in register EBX and adds to this four times the content of EDI. So what's

happening is I get one addition and one multiplication in one single instruction. The reason why

this is fast on a PC is we have dedicated address generation units. These are functional

units within the CPU which are just there to compute memory addresses and these are

there because x86 CPUs are basically SISC CPUs but back then the new RISC CPU set, we

won't do this. These address generation units take up space on the CPU and we could probably

use this better. So besides small instruction sets, address calculation is now a user burden.

Also all operands have to be given in registers. The only exception is load and store instructions.

Only those are allowed to access memory. On an x86 CPU I'm allowed to address memory for